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  www.irf.com 1 12/03/04 irfr3518pbf IRFU3518PBF hexfet   power mosfet v dss r ds(on) max i d 80v 29m  30a parameter max. units v ds drain-to-source voltage 80 v v gs gate-to-source voltage 20 i d @ t c = 25c continuous drain current, v gs @ 10v 38 i d @ t c = 100c continuous drain current, v gs @ 10v 27 a i dm pulsed drain current  150 p d @t c = 25c power dissipation 110 w linear derating factor 0.71 w/c dv/dt peak diode recovery dv/dt  5.2 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c absolute maximum ratings notes   through  are on page 10  applications high frequency dc-dc converters  lead-free benefits low gate-to-drain charge to reduce switching losses fully characterized capacitance including effective c oss to simplify design, (see app. note an1001) fully characterized avalanche voltage and current d-pak irfr3518 i-pak irfu3518 parameter typ. max. units r jc junction-to-case CCC 1.4 r ja junction-to-ambient (pcb mount)  CCC 40 c/w r ja junction-to-ambient CCC 110 thermal resistance downloaded from: http:///
2 www.irf.com 
 dynamic @ t j = 25c (unless otherwise specified) static @ t j = 25c (unless otherwise specified) parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 80 CCC CCC v v gs = 0v, i d = 250a ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.09 CCC v/c reference to 25c, i d = 1ma  r ds(on) static drain-to-source on-resistance CCC 24 29 m ? v gs = 10v, i d = 18a  v gs(th) gate threshold voltage 2.0 CCC 4.0 v v ds = v gs , i d = 250a CCC CCC 20 a v ds = 80v, v gs = 0v CCC CCC 250 v ds = 64v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 200 v gs = 20v gate-to-source reverse leakage CCC CCC -200 na v gs = -20v i gss i dss drain-to-source leakage current parameter min. typ. max. units conditions g fs forward transconductance 34 CCC CCC s v ds = 25v, i d = 18a q g total gate charge CCC 37 56 i d = 18a q gs gate-to-source charge CCC 11 CCC nc v ds = 40v q gd gate-to-drain ("miller") charge CCC 12 CCC v gs = 10v  t d(on) turn-on delay time CCC 12 CCC v dd = 40v t r rise time CCC 25 CCC i d = 18a t d(off) turn-off delay time CCC 37 CCC r g = 9.1 ? t f fall time CCC 13 CCC v gs = 10v  c iss input capacitance CCC 1710 CCC v gs = 0v c oss output capacitance CCC 270 CCC v ds = 25v c rss reverse transfer capacitance CCC 33 CCC pf ? = 1.0mhz c oss output capacitance CCC 1780 CCC v gs = 0v, v ds = 1.0v, ? = 1.0mhz c oss output capacitance CCC 170 CCC v gs = 0v, v ds = 64v, ? = 1.0mhz c oss eff. effective output capacitance CCC 330 CCC v gs = 0v, v ds = 0v to 64v  ns parameter typ. max. units e as single pulse avalanche energy  CCC 160 mj i ar avalanche current  CCC 18 a e ar repetitive avalanche energy  CCC 11 mj avalanche characteristics s d g parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode)  CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 18a, v gs = 0v  t rr reverse recovery time CCC 77 CCC ns t j = 25c, i f = 18a q rr reverse recoverycharge CCC 210 CCC nc di/dt = 100a/s   t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) diode characteristics 38 150  downloaded from: http:///
www.irf.com 3 
 fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 0.01 0.1 1 10 100 1000 0.1 1 10 100 20s pulse width t = 25 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 0.1 1 10 100 1000 0.1 1 10 100 20s pulse width t = 175 c j top bottom vgs 15v 10v 8.0v 7.0v 6.0v 5.5v 5.0v 4.5v v , drain-to-source voltage (v) i , drain-to-source current (a) ds d 4.5v 4.0 6.0 8.0 10.0 12.0 14.0 16.0 v gs , gate-to-source voltage (v) 1.00 10.00 100.00 1000.00 i d , d r a i n - t o - s o u r c e c u r r e n t ( ) t j = 25c t j = 175c v ds = 25v 20s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 r , drain-to-source on resistance (normalized) ds(on) v = i = gs d 10v 38a 
  
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4 www.irf.com 
 fig 8. maximum safe operating area fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0.1 1 10 100 1000 0.0 0.5 1.0 1.5 2.0 v ,source-to-drain voltage (v) i , reverse drain current (a) sd sd v = 0 v gs t = 175 c j t = 25 c j 1 10 100 1000 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) tc = 25c tj = 175c single pulse 1msec 10msec operation in this area limited by r ds (on) 100sec 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 1 02 03 04 0 q g total gate charge (nc) 0 2 4 6 8 10 12 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 40v v ds = 64v v ds = 16v i d = 18a downloaded from: http:///
www.irf.com 5 
 fig 10a. switching time test circuit v ds 9 0% 1 0% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms   
 1     0.1 %          + -   fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response) 25 50 75 100 125 150 175 0 10 20 30 40 t , case temperature ( c) i , drain current (a) c d limited by package downloaded from: http:///
6 www.irf.com 
 q g q gs q gd v g charge d.u.t. v d s i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v 25 50 75 100 125 150 175 0 80 160 240 320 starting tj, junction temperature ( c) e , single pulse avalanche energy (mj) as i d top bottom 7.3a 13a 18a downloaded from: http:///
www.irf.com 7 
 p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop r e-applied v oltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfet   power mosfets
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8 www.irf.com 
  

  

  12 in the assembly line "a" ass embled on ww 16, 1999 example: with assembly t his is an irfr120 lot code 1234 year 9 = 199 9 dat e code we e k 16 part number logo int ernational rect ifier as s e mb l y lot code 916a irfu120 34 year 9 = 1999 dat e code or p = de s i gnat e s l e ad- f r e e product (optional) note: "p" in assembly line position i ndi cates "l ead-f r ee" 12 34 week 16 a = as s e mb l y s i t e code part number irfu120 line a logo lot code as s e mb l y int ernational rect ifier downloaded from: http:///
www.irf.com 9 
  
    

 

 
 
  
  as s e mb l y example: wi t h as s e mb l y this is an irfu120 ye ar 9 = 199 9 dat e code line a we e k 19 in the assembly line "a" as s e mbled on ww 19, 1999 lot code 5678 part number 56 irf u120 international logo rectifier lot code 919a 78 note: "p" in as s embly line pos i ti on i ndi cates "l ead- f r ee"  56 78 assembly lot code rectifier logo international irf u120 part number week 19 dat e code ye ar 9 = 1999 a = assembly site code p = designates lead-free product (opt ional) downloaded from: http:///
10 www.irf.com 
   repetitive rating; pulse width limited by max. junction temperature.   starting t j = 25c, l = 0.99mh r g = 25 ? , i as = 18a.  i sd 18a, di/dt 360a/s, v dd v (br)dss , t j 175c.  pulse width 300s; duty cycle 2%. 
 c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss .  when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniques refer to application note #an-994. data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 12/04  

   

 

 
  tr 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) 12.1 ( .476 ) 11.9 ( .469 ) feed direction feed direction 16.3 ( .641 ) 15.7 ( .619 ) trr trl n otes : 1 . controlling dimension : millimeter. 2 . all dimensions are shown in millimeters ( inches ). 3 . outline conforms to eia-481 & eia-541. notes : 1. outline conforms to eia-481. 16 mm 13 inch downloaded from: http:///
note: for the most current drawings please refer to the ir website at: http://www.irf.com/package/ downloaded from: http:///


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